Why do I see a Bit Error Rate (BER) of 1 after drawing an eye in the Intel® Transceiver Toolkit when using Intel Stratix® 10 E-Tile transceivers? - Why do I see a Bit Error Rate (BER) of 1 after drawing an eye in the Intel® Transceiver Toolkit when using Intel Stratix® 10 E-Tile transceivers? Description Due to a problem with the error counter registers of the Intel® Stratix® 10 E-Tile transceivers, you might see a BER of 1 after drawing an eye in the Intel Transceiver Toolkit. You might also see the following message in the Transceiver Toolkit message pane. "Hard PRBS checker error counter has saturated. The checker has been stopped." Resolution To work around this problem, reprogram the Intel® Stratix® 10 FPGA. Custom Fields values: ['novalue'] Troubleshooting FB: 559350; False ['Stratix® 10 E-Tile Transceiver Native PHY'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 18.0 ['Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']