Wait Statement must contain condition - Wait Statement must contain condition Hello, I am very new to FPGA and VHDL etc... I am trying to get my first code to work on Quartus Prime Lite in VHDL. It is a simple "Hello World" code (see below). entity VHDLTuto is end entity; architecture sim of VHDLTuto is begin process is begin report "Hello World!"; wait; end process; end architecture; I get the following error : Error (10533): VHDL Wait Statement error at VHDLTuto.vhd(11): Wait Statement must contain condition clause with UNTIL keyword I haven't found any reason for this error to appear. Is it a problem when creating the project? Or is it a problem when installing the software ? Any help would be highly appreciated. Thank you Replies: Re: Wait Statement must contain condition I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you. Best Regards, Richard Tan p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey. Replies: Re: Wait Statement must contain condition Hallelujah! I understand now, my bad I got mixed up with the softwares. Thank you very much this will help me a lot! Replies: Re: Wait Statement must contain condition You're trying to compile in Quartus, which is trying to synthesize the design into hardware, which is the goal of the compiler. If you want to just run simulations, you have to compile and run the sim in a simulation tool, like ModelSim or Questasim. Replies: Re: Wait Statement must contain condition Thank you for your reply. Ok if I understood correctly my error comes from the fact that my code would not work on an actual hardware. I am following this tutorial : https://vhdlwhiz.com/basic-vhdl-tutorials/ And since I don't have any hardware I was just trying to do simulations. From the tutorial the "wait until" doesn't seem to be an issue. Why so? Do I need to do an extra step? Thank you in advance Replies: Re: Wait Statement must contain condition An FPGA is not a processor (on its own). You are using commands that may work in a simulation (or a program running on a processor), but these will not turn into hardware in the FPGA. You have to write RTL code to implement the logic function you want to implement on the FPGA. An FPGA "hello world" type of design would be creating a simple adder and running a simulation on it or programming the device and running the design in hardware. The specific error you are seeing is that "wait" can be used to synthesis hardware if "until" is used along with it. In other words, in hardware, you can't have the possibility of the hardware waiting forever. But no matter what, this code is not synthesizable into an FPGA.