Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example (Packet Generate/Check variant) fail when using Siemens Questa* simulator in Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1? - Why does simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example (Packet Generate/Check variant) fail when using Siemens Questa* simulator in Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1? Description Due to a problem in the Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1, simulation of the F-Tile Multi Channel DMA FPGA IP for PCI Express* Design Example with the Packet Generate/Check variant may fail when using the Siemens Questa* simulator. The failure is observed after the DMA queue reset sequence finishes, and a PIO register write is issued. Simulation then stalls with no further activity and terminates with an inactivity timeout after some time. An example of the messages observed in the simulation log is shown below: INFO: 43000 ns H2D: Got Status for Channel 0 INFO: 43000 ns D2H: Performing Channel 0 Queue Reset INFO: 47000 ns D2H: Channel 0 Queue Reset...done INFO: 47000 ns PIO_WRITE_REG 8000000100001000 FATAL: 4000000 ns Simulation stopped due to inactivity! FAILURE: Simulation stopped due to Fatal error! FAILURE: Simulation stopped due to error! ** Note: $stop : ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v(146) Time: 4 ms Iteration: 3 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/g_bfm/p_dut_ep/altpcietb_bfm_top_rp/g_bfm/u1/rp/inst/apps/genblk1/drvr Break at ../../../ip/pcie_ed_sim_tb/dut_pcie_tb_ip/intel_pcie_ftile_tbed_100/sim/altpcietb_g3bfm_log.v line 146 This issue affects simulation only and does not impact hardware functionality. Resolution To work around this problem, generate the F-Tile Multi Channel DMA FPGA IP for PCI Express Design Example (Packet Generate/Check variant) and run simulation using Quartus® Prime Pro Edition Software version 25.1.1. The problem is not observed in that release. There is no other workaround for Quartus® Prime Pro Edition Software versions 25.3.1 and 26.1. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: Troubleshooting QS-50230 novalue ['Interfaces PCIe Multi-Channel DMA (Primary)'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.3.1 ['Agilex® 7 FPGAs and SoCs'] ['Simulation Dev Tools Questa']