Why do I see setup timing violations in my QDR II interface when Rapid Recompile is enabled in my Quartus II project? - Why do I see setup timing violations in my QDR II interface when Rapid Recompile is enabled in my Quartus II project? Description Due to a problem with the Rapid Recompile feature in the Quartus® II software versions 11.0 SP1 and earlier, you may see setup timing violations in your QDR II interface on paths crossing from the DDIO input registers (implemented in the I/O Cell) to the core of the FPGA. An example of a typical failing path is shown below: From: <project hierarchy> |memphy_top_inst|umemphy|uio_pads|uread_pads|read_capture[0].uread_dq_dqs|input_dq_3_ddio_in_inst|regouthi To: <project hierarchy> |memphy_top_inst|umemphy|uread_datapath|read_buffering[0].read_subgroup[1].uread_fifo|data_stored* To avoid this problem, turn off the Rapid Recompile feature. This problem is scheduled to be fixed in a future version of the Quartus II software. Resolution Related Articles Why do my manually-instantiated LCELL components get removed during compilation when Rapid Recompile is turned on? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']