Why does the Altera Serial RapidIO IP insert more than 31 /A/ characters during IDLE1 sequence? - Why does the Altera Serial RapidIO IP insert more than 31 /A/ characters during IDLE1 sequence?
Description An issue has been identified where the Altera® Serial RapidIO® IP can insert mode than the specified maximum of 31 /A/ characters during an IDLE1 sequence. Whilst no interoperability of physical problems has been identified as a result of this behavior, this issue is technically not in line with the specification. Resolution This issue shall be resolved in a future release of the Altera Serial RapidIO IP.
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Troubleshooting
72570
False
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['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA']
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['novalue'] - 2023-03-30
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