Why do I observe read errors with my UniPHY based memory controller IP after migrating the IP to a different version of the Quartus II software? - Why do I observe read errors with my UniPHY based memory controller IP after migrating the IP to a different version of the Quartus II software? Description You must run the pin_assignment.tcl script after migrating the UniPHY based memory controller IP to a different version of the Quartus® II software. Newer versions of the Quartus II software may introduce additional assignments. Without these assignments, the UniPHY based memory controller IP may not function correctly. Resolution Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']