Why do I get a link loss after applying a soft reset, and before o_rx_pcs_ready is available in the Agilex™ 7 F-tile Ethernet Hard IP? - Why do I get a link loss after applying a soft reset, and before o_rx_pcs_ready is available in the Agilex™ 7 F-tile Ethernet Hard IP? Description Due to an unexpected behavior in the Agilex™ 7 F-tile Ethernet Hard IP 25G variant, there is a frequency mismatch between o_clk_rec_di v and o_clk_revc_div64 . Hence, you will observe a loss in the link for one clock cyreset sequence, and before o_rx_pcs_ready is available in the Agilex™ F-Tile Ethernet Hard IP 25G variant. Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.2. Custom Fields values: ['novalue'] Errata 15015366734 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']