Timing problem with internal oscillator: minimum pulse width violation (tch) - Timing problem with internal oscillator: minimum pulse width violation (tch) Hi, I have a system on a Cyclone 10 LP where I use the clock from the internal oscillator for some operations, and I have an external clock that I use for some other operations. For the internal oscillator, I used the IP altera_int_osc (where I cannot program anything). The frequency is 80 MHz by default, as mentioned in the application note AN 496: Using the Internal Oscillator IP Core . This clock is used to drive some counters, which will toggle some signals that are going out of the FPGA. Therefore, I don't have any signal driven by the internal oscillator clock that is used somewhere else in the system. In the sdc file, I constrained the clock coming from the internal oscillator as follows: create_clock [get_pins {altera_int_osc_inst|sd1|clkout}] -name {int_osc_clk} -period 12.5 -waveform { 0 6.25 } where altera_int_osc_inst is the instance of the IP, clkout the name of the output of the IP, sd1 is the node name of the clock, int_osc_clk is the name of my clock signal coming from the IP, and 12.5 ns = 1 / 80 MHz. After compilation, Quartus tells me "Timing requirements not met". In the Timing analyzer report, under the Fmax Summary tab, I see : Restricted Fmax: 45.49 MHz Note: limit due to high minimum pulse width violation (tch) In the Timing analyzer report, under the Minimum Pulse Width Summary, I see : Slack : -8.730 End Point TNS : -18.1 As a test, I simplified my block such that it contains only a shift register with its LSB going out of the FPGA, and I still have the same problem. Therefore, the problem in not in the VHDL design using the internal oscillator clock. I guess it is either my sdc file that is incorrect or something else, but I cannot see what. Any help is more than welcome. Thanks, Jérôme Replies: Re: Timing problem with internal oscillator: minimum pulse width violation (tch) You can ignore this violation for now. Let me know if you have further question? Replies: Re: Timing problem with internal oscillator: minimum pulse width violation (tch) Thanks for your reply. Replies: Re: Timing problem with internal oscillator: minimum pulse width violation (tch) Thanks, this should be a bug. we will report it to the developer. Replies: Re: Timing problem with internal oscillator: minimum pulse width violation (tch) I am using Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition. Replies: Re: Timing problem with internal oscillator: minimum pulse width violation (tch) I forgot to ask you are using which version of Quartus? Pro or std? Replies: Re: Timing problem with internal oscillator: minimum pulse width violation (tch) Hi Kenny, Thanks for your fast answer. Attached you can find the project archive. Jérôme Replies: Re: Timing problem with internal oscillator: minimum pulse width violation (tch) Hi Jerome, can you attached your design.qar files for us to have a look? Thanks, Kenny