Simulation Fails for Stratix V Designs Generated Using SOPC Builder - Simulation Fails for Stratix V Designs Generated Using SOPC Builder
Description Simulation fails when you use the SOPC builder to generate Verilog HDL or VHDL simulation models for designs targeting Stratix V devices. This issue affects all Triple-Speed Ethernet designs targeting Stratix V devices. Resolution No workaround. This issue will be fixed in a future version of the Triple Speed Ethernet MegaCore function.
Custom Fields values:
['novalue']
Troubleshooting
novalue
True
['Ethernet']
['FPGA Dev Tools Quartus II Software']
novalue
10.0
['Programmable Logic Devices']
['novalue']
['novalue']
['novalue'] - 2021-08-25
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