The Hard IP for PCI Express Qsys Example Design Reconfiguration Driver Has Unconnected cal_busy_in Output Signal - The Hard IP for PCI Express Qsys Example Design Reconfiguration Driver Has Unconnected cal_busy_in Output Signal Description Altera provides design examples available in the Quartus Prime or Quartus II installation directories. The Avalon Streaming (Avalon-ST) Qsys example designs include the Transceiver Reconfiguration Controller and the Altera PCIe Reconfig Driver. The cal_busy_in output of the Altera PCIe Reconfig Driver module is unconnected. This signal must be connected for transceiver reconfiguration to work correctly. It is not available in the top-level components of the Qsys system. Resolution Because the cal_busy_in output is not available as a top-level signal, you must connect this signal in the RTL. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']