TSN-EP-10G: 10G TSN Ethernet Endpoint Controller - The TSN-EP-10G is a highly configurable TSN Ethernet Endpoint Controller IP core designed to streamline the implementation of Time-Sensitive Networking endpoints. It provides hardware support for 802… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA The TSN-EP-10G implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking (TSN) standards. It integrates hardware stacks for timing synchronization (802.1AS-2020) and traffic shaping (802.1Qav and 802.1Qbv) and a low-latency Ethernet MAC. Enhanced reliability features can also be supported, using the optional hardware modules for FRER Frame Replication and Elimination for Reliability (802.1CB) and PSFP Per-Stream Filtering and Policing (802.1Qci). The controller core is designed to enable high-precision timing synchronization and flexible yet accurate traffic scheduling. Requiring minimal software assistance for its initialization, it features extremely low and deterministic ingress and egress latencies and simplifies the development of time-aware applications. While operating autonomously, the TSN-EP-10G provides the system with timing information (timestamps, alarms, etc.) that is typically required for the operation of a TSN network endpoint device. Furthermore, it allows the system to define and tune in real time the traffic shaping parameters according to an application’s requirements. The TSN-EP-10G uses standard AMBA® interfaces to ease integration. Its configuration and status registers are accessible via a 32-bit-wide APB bus, and packet data are input and output via 128-bit-wide AXI-Streaming buses. To further expedite and ease the implementation of customer applications, DMA engines providing access to the stream interfaces via a memory-mapped AXI4 master port, and software stacks supporting higher-layer protocols, such as 802.1Qcc, 802.1Qca and SNMP, are optionally available. The TSN-EP is designed with industry best practices and is available in synthesizable RTL source code or as a targeted FPGA netlist. Deliverables provide everything required for a successful implementation, including sample scripts, an extensive testbench, and comprehensive documentation. Ethernet Aerospace Defense Government Industrial Medical Transportation Wireless TSN-EP-10G: 10G TSN Ethernet Endpoint Controller Key Features 802.1AS-2020 FreeRTOS and Linux gPTP stack Offering Brief No Yes No Yes Encrypted Verilog Verilog Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Cyclone® 10 GX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production FreeRTOS,Linux a1JUi0000049U6rMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information TSN-EP-10G a1JUi0000049U6rMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-15T23:32:31.000+0000 The TSN-EP-10G is a highly configurable TSN Ethernet Endpoint Controller IP core designed to streamline the implementation of Time-Sensitive Networking endpoints. It provides hardware support for 802.1AS-2020, 802.1Qav, 802.1Qbv, optional 802.1Qci and 802.1Qcc. It includes a low-latency Ethernet MAC with XGMII PHY interface and AXI-Stream Host interface. The core delivers precise, deterministic latencies with minimal host software required and provides real-time timing information along with dynamic traffic-shaping adjustments. Designed for simple integration, TSN-EP-10G uses standard AMBA® interfaces: a 32-bit APB for CSR and a 128-bit AXI-Streaming interface for data packets. Optional DMA is also available. Delivered as synthesizable RTL or FPGA netlist, it includes testbenches, sample scripts, documentation and a lightweight gPTP for FreeRTOS and Linux. Suitable for automotive, industrial, aerospace, and other applications requiring low-latency, deterministic TSN communication. Partner Solutions