Why does the HDMI 2.1 Intel® FPGA Design Example occasionally fail to read the HDMI sink receiver EDID after a hotplug or reset event? - Why does the HDMI 2.1 Intel® FPGA Design Example occasionally fail to read the HDMI sink receiver EDID after a hotplug or reset event? Description Due to a problem starting in version 19.4 of the Intel® Quartus® Prime Pro software when using the Intel® Arria® 10 Devices, and version 20.4 of the Intel® Quartus® Prime Pro software when using the Intel® Stratix® 10 devices, the HDMI Intel® FPGA Source IP core may fail to read the HDMI sink receiver EDID after a hotplug or reset event. This is due to the HDMI Intel® FPGA Source IP core FLT_update polling timer continuing to run when the HDMI Tx cable is unplugged. This problem causes corruption to I2C master software design and prevents it from being able to correctly read back the EDID content. Resolution This problem is fixed starting from the Intel® Quartus® Prime Pro Edition version 21.1 software. Custom Fields values: ['novalue'] Troubleshooting 1508828351 True ['HDMI IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 19.4 ['Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']