Why does the Stratix® 10 25G Ethernet IP core receive random erroneous packets in open ended condition? - Why does the Stratix® 10 25G Ethernet IP core receive random erroneous packets in open ended condition? Description In rare cases, the Stratix® 10 25G Ethernet IP core may still receive random erroneous packets when operating in open ended condition, i.e. there is no fiber or QSFP28 module connected. Resolution A workaround for this problem is to edit the SYNOPT_STRICT_SOP parameter in the top level IP wrapper file to 1 . This workaround is only available for designs with Preamble Pass-Through feature disabled. Locate the 25G Ethernet IP variant wrapper file at /synth/<file_name>.v . At the instantiation of the version specific 25G Ethernet IP, change the SYNOPT_STRICT_SOP parameter setting from (0) to (1) . Do not regenerate the 25G Ethernet IP core. Compile your design. Example design IP variant file at /synth/ex_25g.v : ex_25g_alt_e25s10_191_dyjat6a #( .SYNOPT_READY_LATENCY (0), .SYNOPT_CORE_VAR (0), .SYNOPT_KHZ_REF_EN (0), .SYNOPT_RSFEC (0), .SYNOPT_DIV40 (1), .SYNOPT_LINK_FAULT (0), . SYNOPT_STRICT_SOP (1) , .SYNOPT_PREAMBLE_PASS (0), Please note that you may observe junk data on the 64-bit l1_rx_data bus. The l1_rx_valid should be used as an indicator to accept or ignore the data. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 2206125409 False ['25G Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.4 19.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']