Timing Violations when tx_rdp and rx_rdp Clocks are Not Synchronized to Core Clock in SerialLite II IP Core - Timing Violations when tx_rdp and rx_rdp Clocks are Not Synchronized to Core Clock in SerialLite II IP Core Description The SerialLite II IP core no longer supports V and 10 series device families. Therefore, the sdc constraints in the generated .sdc file are no longer valid. You will encounter the following warning message: Ignored filter at SLII_instance.sdc(136): *SLII_instance*transmit|clkout could not be matched with a clock Ignored filter at SLII_instance.sdc(136): *SLII_instance*receive|clkout could not be matched with a clock Ignored filter at SLII_instance.sdc(137): *SLII_instance*rx[0]|clkout could not be matched with a clock Resolution You have to modify the set_clock_groups constraints to set the correct clock assignments. Set the SerialLite II IP core tx_rdp/rx_rdp/rx_hpp/tx_hpp clocks to be mutually exclusive to the recovered clock and the transceiver transmit clock. For example, when using an Arria V device with tx_rdp or rx_rdp clock, modify these constraints as shown below: set_clock_groups -asynchronous -group { *custom_phy_inst*inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk } -group { *custom_phy_inst*inst_av_hssi_8g_rx_pcs|wys|rcvdclkpma } set_clock_groups -asynchronous -group { *custom_phy_inst*inst_av_hssi_8g_rx_pcs|wys|rcvdclkpma } -group [get_clocks ] set_clock_groups -asynchronous -group [get_clocks ] -group { *custom_phy_inst*inst_av_hssi_8g_tx_pcs|wys|txpmalocalclk} Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 15.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']