Why does my transceiver RTL simulation fail to assert rx_is_lockedtodata when in internal serial loopback with Intel® Stratix 10 L/H-Tile, Arria® 10, and Cyclone® 10 GX devices? - Why does my transceiver RTL simulation fail to assert rx_is_lockedtodata when in internal serial loopback with Intel® Stratix 10 L/H-Tile, Arria® 10, and Cyclone® 10 GX devices? Description An undefined “x” signal on the transceiver rx_serial_data port may cause the rx_is_lockedtodata signal to fail to assert when performing RTL simulation of Intel Stratix 10 L/H-Tile, Arria 10, and Cyclone 10 GX devices. Resolution To perform RTL simulation of transceiver internal serial loopback, ensure that a defined state of ‘0’ or ‘1’ is applied to the transceiver rx_serial_data port in your testbench. This prevents “x” propagation into the simulation model. The ‘0’ or ‘1’ from the rx_serial_data port will be ignored when the transceiver internal serial loopback switch is enabled. Custom Fields values: ['novalue'] Troubleshooting 18015426513 False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 20.4 ['Arria® 10 FPGAs and SoCs', 'Cyclone® 10 FPGAs', 'Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']