Why does my Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP with 25 Gbps lanes fail timing closure when targeting an Intel® Stratix® 10 E-tile Engineering Sample (ES) device? - Why does my Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP with 25 Gbps lanes fail timing closure when targeting an Intel® Stratix® 10 E-tile Engineering Sample (ES) device? Description Variants of the Interlaken (2nd Generation) Intel® Stratix® 10 FPGA IP with 25 Gbps lanes do not support Engineering Sample (ES) devices. Resolution To obtain the best “Quality of Result” for timing closure, launch Design Space Explorer II in the Intel® Quartus® Prime Software and perform a seed sweep. Custom Fields values: ['novalue'] Troubleshooting 1507049399 True ['Interlaken (2nd Generation) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 18.1.1 ['Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']