Why is the captured register waveform in SignalTap II Logic Analyzer inverted from the expected signal value? - Why is the captured register waveform in SignalTap II Logic Analyzer inverted from the expected signal value? Description You may see this behavior when you tap post-fit nodes in the SignalTap™ Logic Analyzer if the register has been implemented with NOT gate push back. This is the correct behavior. Resolution To avoid this behavior, tap the pre-synthesis register instead. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']