Why does my Transceiver Reconfiguration Controller Intel® FPGA IP generate Verilog HDL warnings? - Why does my Transceiver Reconfiguration Controller Intel® FPGA IP generate Verilog HDL warnings? Description Due to a problem in the Quartus® II software version 12.1 and later, you might see the following warnings during Analysis & Synthesis when compiling designs containing the Stratix® V Transceiver Reconfiguration Controller Intel FPGA IP: Warning (10268): Verilog HDL information at alt_xcvr_reconfig_soc.sv(169): always construct contains both blocking and non-blocking assignments Warning (10268): Verilog HDL information at alt_xcvr_reconfig_dfe_adapt_tap_sv.sv(302): always construct contains both blocking and non-blocking assignments Resolution These warnings are safe to ignore. If you wish to avoid the warnings, edit the files generated by the parameter editor to change the blocking assignments to non-blocking assignments at the indicated line numbers. For example, the line mgmt_ram_offset = {RAM_BITS{1\'b0}}; should be changed to mgmt_ram_offset <= {RAM_BITS{1\'b0}}; ; Also, the line ctrl_wdata = save_ctrl_reg13; should be changed to ctrl_wdata <= save_ctrl_reg13; This problem is fixed in the Quartus II software version 13.0 SP1. Custom Fields values: ['novalue'] Troubleshooting 2205799164 False ['Transceiver Native PHY Intel® Stratix® V FPGA IP'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']