Can I drive the pld_clk with a clock source other than coreclkout_hip in the Cyclone® V Hard IP for PCI Express*? - Can I drive the pld_clk with a clock source other than coreclkout_hip in the Cyclone® V Hard IP for PCI Express*? Description In the Cyclone® V Hard IP for PCI Express* User Guide version 1.5 and earlier, you might see the description on pld_clk : " You must drive this clock with coreclkout_hip .". However, in the Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide version 18.0, you might see the description on pld_clk : " You can drive this clock with coreclkout_hip. If you drive pld_clk with another clock source, it must be equal to or faster than coreclkout_hip, but cannot be faster than 250 MHz. Choose a clock source with a 0 ppm accuracy if pld_clk operates at the same frequency as coreclkout_hip. ". Resolution Yes, you can drive pld_clk with another clock source. Follow the description of pld_clk in the Cyclone® V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide version 18.0. This information will be updated in a future release of the Cyclone® V Hard IP for PCI Express* User Guide. Custom Fields values: ['novalue'] Troubleshooting 16024187841 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 20.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['Cyclone® FPGA Dev Kit']