Why does the Intel Agilex® 7 FPGA portfolio Development Kit fail to link train in a PCIe* Gen3 system correctly? - Why does the Intel Agilex® 7 FPGA portfolio Development Kit fail to link train in a PCIe* Gen3 system correctly? Description The Intel Agilex® 7 FPGA portfolio Development Kit has (SW7.1) a default position set to ON. SRIS Mode. This can cause PCIe* link instability problems, especially in older Gen3 systems. Resolution To work around this potential problem, set SW7.1 to the OFF position (Common Refclk architecture), especially when using the card in older Gen3 systems. Custom Fields values: ['novalue'] Troubleshooting 22011800456 False ['novalue'] ['novalue'] novalue novalue ['Agilex™ 7 FPGA F-Series'] ['novalue'] ['novalue'] ['Agilex™ 7 FPGA F-Series Dev Kit']