Why does Quartus® report errors when HPS SPI signals are routed to FPGA pins for Agilex™ 5 FPGA devices in Quartus® Prime Pro Edition Software version 24.2? - Why does Quartus® report errors when HPS SPI signals are routed to FPGA pins for Agilex™ 5 FPGA devices in Quartus® Prime Pro Edition Software version 24.2? Description Due to a problem in Quartus® Prime Pro Edition Software version 24.2, when HPS SPI signals are routed to FPGA pins, you may get the Quartus Fitter compilation errors related to the SPI signals. For Example: Error (14986): After placing as many components as possible, the following errors remain: Error (175001): The Fitter cannot place 1 pin. Info (14596): Information about the failing component(s): Info (175028): The pin name(s): subsys_hps_agilex_hps_spim0_sclk_out_clk Resolution Please use HPS IOs for HPS SPI signals as an alternative. Additional Information This problem is fixed in Quartus® Prime Pro Edition Software 25.1.1 version. Custom Fields values: ['novalue'] Troubleshooting 16024153118 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1.1 24.2 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']