Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks - Warning (177007): PLL(s) placed in location <PLL location> do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks Description You might see this warning in the Quartus® II software design fitter report if a phase locked loop (PLL) that has the reconfiguration option enabled does not have a compensated clock specified. Resolution To set the PLL compensation targets for the PLL Intel® FPGA IP for reconfigurable PLLs, create a “ Match PLL Compensation Clock ” assignment in the Quartus II Assignment Editor. The syntax of the PLL clock node has to be specific for it to be saved in the Assignment Editor. Filter on *divclk[* in a post compilation filter in the node finder to find the correct name. For example: clkrst:u_clkrst|adc_pll_ip:u_adc_pll_ip|adc_pll_ip_0002:adc_pll_ip_inst|altera_pll:altera_pll_i|altera_cyclonev_pll:cyclonev_pll|divclk[0] Where divclk[0] corresponds to Counter CO in this PLL Intel® FPGA IP instance. This workaround/fix is for PLLs that have the reconfiguration feature enabled. See the related solution for PLLs without the reconfiguration feature enabled. Related Articles How do I set the PLL compensation targets for the Altera_PLL megafunction? Custom Fields values: ['novalue'] Troubleshooting 1408036202 False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']