Horizontal Resolution Limitation for Pixels in Parallel in Video and Image Processing (VIP) IP Cores - Horizontal Resolution Limitation for Pixels in Parallel in Video and Image Processing (VIP) IP Cores Description The Video and Image Processing (VIP) IP cores that offer the pixels in parallel feature have a limitation in the supported resolution widths. The supported resolution widths must divide cleanly by the number of pixels in parallel. For the Clocked Video Output II IP core, this limitation includes the front porch, back porch, and the sync length of the horizontal blanking period for external syncs. The Avalon Streaming (Avalon-ST) video bus does not support “empty pixel locations”. As such, all video resolutions are assumed divisible by 4 (for 4 PIP) or 2 (for 2 PIP). Resolution There is no workaround for this issue. This issue is fixed in version 16.0 of the Video and Image Processing (VIP) IP cores. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']