Why does the Intel® Arria® 10 FPGA Hard IP for PCI Express in Root Port mode, LTSSM not stay in the Disabled state when Link Disable bit is set to 1. - Why does the Intel® Arria® 10 FPGA Hard IP for PCI Express in Root Port mode, LTSSM not stay in the Disabled state when Link Disable bit is set to 1. Description When software sets the Link Disable bit in the Link Control register, the Root Port LTSSM is directed to the Disabled state. Once it enters the Disabled state, it should stay in that state unless the software resets the Link Disable bit. However, when using the Intel® Arria® 10 FPGA Hard IP for PCI Express, the Root Port exits the Disabled state even if the Link Disable bit is set. Resolution There is no workaround for this problem. This problem is not scheduled to be fixed. Custom Fields values: ['novalue'] Troubleshooting FB: 556761; True ['Arria® 10 Cyclone® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 17.1.1 ['Arria® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']