How do I verify the correct frequency of divfwdclk when an incorrect frequency of divfwdclk is shown in the Quartus Prime TimeQuest Timing Report? - How do I verify the correct frequency of divfwdclk when an incorrect frequency of divfwdclk is shown in the Quartus Prime TimeQuest Timing Report? Description The frequency of divfwdclk shown in Quartus ® Prime TimeQuest timing report for certain combinations of data rate and SERDES factor in Stratix ® V devices may be incorrect. For example: Enable Dynamic Phase Alignment Deserialization factor = 10 Input date rate = 150Mpbs Input clock frequency = 150Mhz DPA mode : use divfwdclk The divfwdclk should be 150MHz/10 = 15MHz, but TimeQuest reports a divfwdclk of 30MHz. Resolution To work around this issue, use the create generated clock command in a user SDC file or in the TimeQuest Timing Analyzer to divide the divfwdclk to the correct frequency. For example: create_generated_clock -name divfwdclk -source [get_pins {rx_cmp_inst|ALTLVDS_RX_component|auto_generated|rx_0|dpaclkin[0]}] -divide_by 2 [get_pins {rx_cmp_inst|ALTLVDS_RX_component|auto_generated|rx_0|divfwdclk}] Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']