Agilex™ 5 FPGAs Hard-Processor Subsystem (HPS) Overview - 16 Minutes The Agilex™ 5 FPGA product family extends the innovations of the Agilex FPGA portfolio to midrange FPGA applications. The Agilex 5 FPGAs and SoCs serve a broad range of applications that require high performance, lower power consumption, small form factor, and lower logic densities. This training introduces the multicore Arm* processors present in Agilex 5 FPGAs including a dual-core Arm* Cortex* A76 and a dual-core Arm* Cortex* A55 processor. It also describes the unique features of the peripherals present in the HPS. Course Objectives At course completion, you will be able to: Understand the details of dual-core Arm* Cortex A76 MPCore and dual-core Arm* Cortex* A55 MPCore processor units available in Agilex FPGAs Explore external SDRAM and flash memory interfaces for HPS Learn about the features of the interconnect to logic core bridges Skills Required Background in digital logic design Basic knowledge of SoC FPGA design Familiarity with the Quartus® Prime Design Software If the audio for the course does not start automatically, press pause and then play on the course player. A transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OAG5HPS. FPGA_OAG5HPS. <p>Agilex 5 FPGAs Hard-Processor Subsystem (HPS) Overview</p>