Timing Closure for Hard LPDDR2 Interfaces May Not be Robust in Cyclone V SoC Devices - Timing Closure for Hard LPDDR2 Interfaces May Not be Robust in Cyclone V SoC Devices Description This problem affects LPDDR2 products. Hard LPDDR2 interfaces targeting Cyclone V SoC devices may have difficulty achieving timing closure. Resolution There is no workaround for this issue. This issue is fixed in release 13.1. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 12.1.1 ['Cyclone® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']