Why does the CPL_ERR signal not toggle the appropriate error status bits in the Configuration Space registers? - Why does the CPL_ERR signal not toggle the appropriate error status bits in the Configuration Space registers? Description Due to a problem with the Altera® Hard IP for PCI Express® in Arria® V and Cyclone® V devices, toggling the cpl_err signal will not log the error in the Error Status registers. This issue affects all cpl_err[*] signals, but does not affect the cpl_err_func signals. Resolution Application Layer logic must perform an LMI write to the appropriate error register, and create the appropriate TLP, to workaround the issue described. See Table 2-29 Completion Status Field Values, in the PCI Express Base 3.0 Specification. This problem is not scheduled to be fixed in a future Quartus® II software release. Custom Fields values: ['novalue'] Troubleshooting 81272 False ['Avalon-MM Arria® V Hard IP for PCI Express IP'] ['FPGA Dev Tools Quartus II Software'] 14.0 11.0.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA'] ['novalue'] ['novalue'] ['novalue']