Why does the Altera LVDS SERDES IP in Tx mode fail to generate the VHDL simulation model? - Why does the Altera LVDS SERDES IP in Tx mode fail to generate the VHDL simulation model?
Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 17.0 and later, you may see the Altera LVDS SERDES IP fails to generate. This problem occurs when the IP is in Tx mode, and you have selected VHDL for the simulation model. Resolution To work around this problem, generate the simulation model in Verilog HDL. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.
Custom Fields values:
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Troubleshooting
FB: 468437;
False
['LVDS SERDES IP']
['FPGA Dev Tools Quartus® Prime Software Pro']
17.1
17.0
['Arria® 10 FPGAs and SoCs']
['novalue']
['novalue']
['novalue'] - 2023-01-12
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