Why might the Agilex™ 7 FPGA device fail to configure or reconfigure? - Why might the Agilex™ 7 FPGA device fail to configure or reconfigure? Description Due to a problem in the Quartus® Prime Pro Edition Software v21.3 and later, Agilex™ 7 FPGA devices may fail to configure if an unstable clock signal is applied to the System PLL 0 or System PLL 2 during device configuration. Resolution To work around this problem, ensure that used F-Tile System PLL 0 and System PLL 2 reference clock signals in your design are correct and stable before the device configuration begins. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 1508892844 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 21.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']