Warping Engine IP Core - Memory -to memory or memory to stream Warping engine for projectors, fish-eye lense correction or Head Up Displays (HUDs). TES Electronic Solutions (TES) is a premier full-spectrum design house and innovative technology provider, specialized in delivering high-complexity embedded systems and silicon-proven IP as a long… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® III Bare Die Cyclone® III FPGA Cyclone® III LS FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA HardCopy™ II ASIC Devices HardCopy™ III ASIC Devices MAX® 10 FPGA MAX® V CPLD Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA eASIC™ N3X Devices eASIC™ N3XS Devices eASIC™ N5X Devices easicopy™ TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory to memory or memory to AXI4 Stream. Applications are for example pre-warping for projection on head-up displays (HUDs) or fisheye-correction of camera images. The image transformation is controlled via a highly compressed Look Up Table (LUT) allowing arbitrary transformations. The IP core adapts to different bus interfaces like AMBA APB and AHB/AXI as well as the Altera Avalon bus interface at different bus width. Video and Image Processing Aerospace ASIC Proto Consumer Defense Industrial Medical Transportation Warping Engine IP Core Key Features Image warping / transformation Offering Brief No No No No C/C++ Encrypted VHDL VHDL Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 Bare Die Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® III Bare Die Cyclone® III FPGA Cyclone® III LS FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA HardCopy™ II ASIC Devices HardCopy™ III ASIC Devices MAX® 10 FPGA MAX® V CPLD Stratix® 10 AX FPGA Stratix® 10 Bare Die Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Stratix® III FPGA Stratix® IV E FPGA Stratix® IV GT FPGA Stratix® IV GX FPGA Stratix® V E FPGA Stratix® V GS FPGA Stratix® V GX FPGA eASIC™ N3X Devices eASIC™ N3XS Devices eASIC™ N5X Devices easicopy™ Yes No 24.1.0 Offering Brief Production bare metal,Linux a1JUi0000049UPxMAM What's Included QSys component Ordering Information Warping Engine a1JUi0000049UPxMAM Production Intellectual Property (IP) a1MUi00000BO8tXMAT a1MUi00000BO8tXMAT Select 2026-05-13T22:57:18.000+0000 Memory -to memory or memory to stream Warping engine for projectors, fish-eye lense correction or Head Up Displays (HUDs). Partner Solutions