Why does the Agilex® 7 FPGA HPS EMIF and fabric EMIF hang after core reconfiguration when both interfaces share the same IO bank in x72 configuration? - Why does the Agilex® 7 FPGA HPS EMIF and fabric EMIF hang after core reconfiguration when both interfaces share the same IO bank in x72 configuration? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when Agilex® 7 FPGA F-Series and I-Series HPS EMIF and fabric EMIF share the same IO bank in x72 configuration and the design operates in HPS-first mode, the initial configuration can succeed, but subsequent core reconfigurations can cause the fabric EMIF calibration firmware to hang for designs targeting in Agilex® 7 FPGA F-Series and I-Series devices. The observed failure signature is that, after the FPGA is reconfigured without a full board power cycle, the fabric EMIF no longer responds correctly and the calibration flow does not assert cal_success or cal_fail . Resolution A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.2. Download and install patch 0.70fw below. quartus-24.2-0.70fw-li nux.zip quartus-24.2-0.70fw-rea dme.zip quartus-24.2-0.70fw-wind ows.zip This problem is scheduled to be resolved in a future release of the Quartus® Prime Pro Edition Software. Custom Fields values: Errata CEG-57625 novalue ['Memory Controllers'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 24.2 ['Agilex® 7 FPGA I-Series', 'Agilex® 7 FPGA F-Series']