Error: Verilog HDL Procedural Assignment error at <file name>.v(): illegal Procedural Assignment to nonregister data type <signal name> - Error: Verilog HDL Procedural Assignment error at <file name>.v(): illegal Procedural Assignment to nonregister data type <signal name> Description This error will occur in the Quartus ® II software version 3.0 if you have made an illegal assignment to a signal that is not a reg data type. In the Verilog language, certain signal assignments can only be made to reg data signals, not wire data signals. Quartus II software versions lower than 3.0 did not enforce this wire/reg checking, although it is correct enforcement of the Verilog language. Therefore you may get errors in version 3.0 on designs that passed in version 2.2 or lower. To eliminate this error, add a register declaration for this signal to comply with the Verilog HDL standard. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']