Why does the Modular Scatter-Gather DMA IP fail to generate when using VHDL in Qsys? - Why does the Modular Scatter-Gather DMA IP fail to generate when using VHDL in Qsys? Description Due to a problem in the Quartus® II software version 14.1, the Modular Scatter-Gather DMA (MSGDMA) IP will fail during generation of the simulation model when the simulation language is set to VHDL. Resolution This problem is fixed starting with the Quartus II software version 15.0. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 14.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']