Why does the F-Tile Serial Lite IV FPGA IP RX Simplex Design rx_pcs_ready fail to assert? - Why does the F-Tile Serial Lite IV FPGA IP RX Simplex Design rx_pcs_ready fail to assert? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, for F-Tile Serial Lite IV FPGA IP in RX simplex mode for PMA data rate above 25Gbps under the scenario where the respective TX channel is unused, you will observe RX link-up failure: rx_block_lock: 1'b0 rx_pcs_ready: 1'b0 Resolution To work around this problem, you can use the following two methods: Place a redundant F-Tile Serial Lite IV FPGA IP with TX Simplex mode in the same channel. Change the F-Tile Serial Lite IV FPGA IP to duplex mode. There is no plan to fix the above problem. Custom Fields values: ['novalue'] Troubleshooting 15016006967 False ['F-Tile Serial Lite IV IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue No plan to fix ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']