Can I connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP? - Can I connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP? Description No, you cannot connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP. Resolution If you enable the rx_coreclkin port of the 10GBASE-R PHY IP, the 156.25 MHz rx_coreclkin signal must be generated outside of the IP. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']