Introduction to the Altera® FPGA P-Tile - 29 Minutes Altera® Agilex™ F-Series and Altera® Stratix® 10 DX FPGAs are packaged with Altera's P-Tile transceiver tile, which implements the PCI Express* Gen3 and Gen4 standards. This training is the first step in learning how to build a high-speed interface using the P-Tile. You will begin by learning about Altera's Embedded Multi-Die Interconnect Bridge (EMIB) technology that makes packaging the P-Tile with the FPGA possible. You will then be introduced to the architecture and key features of the P-Tile including endpoint, root port, and transaction layer protocol (TLP) bypass modes, port bifurcation, autonomous hard IP (HIP) mode, and Single Root IO Virtualization (SR-IOV). The functional components of the tile will be described including the PMA, PCS, and configuration registers. Course Objectives At course completion, you will be able to: Describe the Functional blocks found in the P-Tile including the PCS and PMA blocks Understand the clocking configuration of the P-Tile Describe the key features of the P-Tile including TLP bypass mode, port bifurcation, and SR-IOV Skills Required General understanding of transceivers General understanding of PCI Express* Protocol If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OPTILE. FPGA_OPTILE. <p>Introduction to the Altera FPGA P-Tile</p>