How should I set the termination settings when I require HCSL standard on the transceiver REFCLK pin for PCI Express Protocol? - How should I set the termination settings when I require HCSL standard on the transceiver REFCLK pin for PCI Express Protocol? Description The Quartus® II software version 9.1 incorrectly enables internal termination if you set the HCSL IO standard on the transceiver REFCLK pins for Stratix® IV and Arria® II GX devices. You can select this IO standard option only if the transceiver is configured in PCI Express (PIPE) functional mode. Resolution To work around this problem, follow the steps below and use DC coupling with external termination on the clock pin. Add the following assignment to your project .qsf file set_instance_assignment -name INPUT_TERMINATION OFF -to <refclk_pin_name> Re-compile the design This problem is fixed beginning with the Quartus II software version 9.1 SP1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 9.1.1 9.1 ['Arria® II FPGAs', 'Arria® II GX FPGA', 'Stratix® IV FPGAs', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']