Error: Clock Divider node - You may encounter the error in Cyclone® V and Arria® V transceiver devices if you not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY in external PLL mode. - Error: Clock Divider node - You may encounter the error in Cyclone® V and Arria® V transceiver devices if you not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY in external PLL mode. Description Error: Clock Divider node 'inst|altera_xcvr_native_av:txcvr_top_inst|av_xcvr_native:gen_native_inst.av_xcvr_native_insts[0].gen_bonded_group_native.av_xcvr_native_inst|av_pma:inst_av_pma|av_tx_pma:av_tx_pma|av_tx_pma_ch:tx_pma_insts[0].av_tx_pma_ch_inst|tx_pma_ch.tx_cgb' is not properly connected on the 'CLKCDRLOC' port. You may encounter the error above in Cyclone® V and Arria® V transceiver devices if you have not connected the outclk_0 port of your Transceiver PLL to the ext_pll_clk input port of the transceiver Native PHY when in external PLL mode. Custom Fields values: ['novalue'] Troubleshooting novalue False ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA'] ['novalue'] ['novalue'] ['novalue']