JPEG-XL-E JPEG XL Encoder - The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard. Leveraging the advanced coding tools of the JPEG XL standard, the core achieves substantially… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® II GX FPGA Arria® II GZ FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard. Leveraging the advanced coding tools of the JPEG XL standard, the core achieves substantially higher compression efficiency than legacy JPEG while requiring fewer hardware resources than JPEG 2000 and comparable codecs. By incorporating algorithms optimized for human visual perception, it delivers exceptional performance for high dynamic range (HDR) and wide color gamut (WCG) imagery. Thanks to its efficient architecture, the compact encoder core achieves a latency of just one frame and a processing throughput of one sample per clock cycle. A single instance can encode 4K-resolution images in real time, while multiple cores can be instantiated in parallel to support higher resolutions. The JPEG-XL-E core accepts input samples in IEEE 754 single- or half-precision floating-point format and outputs the JPEG XL compressed payload. Designed for ease of integration, the encoder core operates autonomously once configured, requiring no further assistance from the host processor. It provides 64-bit AMBA® AXI manager interfaces for reading uncompressed image data and writing the compressed bitstream to system memory, as well as an APB3 subordinate interface for control and status register access. JPEG-XL-E is designed with industry best practices, and its reliability has been proven through both rigorous verification and extensive prototype testing. Its deliverables include a complete verification environment and a bit-accurate software model. Video and Image Processing Aerospace ASIC Proto Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Test Transportation Wireless JPEG-XL-E JPEG XL Encoder Key Features Higher compression efficiency than JPEG with near-lossless visual quality, reducing bandwidth and storage while preserving image fidelity Offering Brief No No No Yes Encrypted Verilog Verilog Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Arria® II GX FPGA Arria® II GZ FPGA Arria® V GT FPGA Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST FPGA Arria® V SX FPGA Cyclone® 10 GX FPGA Cyclone® 10 LP FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE FPGA Cyclone® V ST FPGA Cyclone® V SX FPGA MAX® 10 FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi000008AslhMAC What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog or FPGA netlist Ordering Information JPEG-XL-E a1JUi000008AslhMAC Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-21T12:58:33.000+0000 The JPEG-XL-E implements an image compression engine compliant to the JPEG XL, ISO/IEC 18181 standard. Leveraging the advanced coding tools of the JPEG XL standard, the core achieves substantially higher compression efficiency than legacy JPEG while requiring fewer hardware resources than JPEG 2000 and comparable codecs. By incorporating algorithms optimized for human visual perception, it delivers exceptional performance for high dynamic range (HDR) and wide color gamut (WCG) imagery. Thanks to its efficient architecture, the compact encoder core achieves a latency of just one frame and a processing throughput of one sample per clock cycle. A single instance can encode 4K-resolution images in real time, while multiple cores can be instantiated in parallel to support higher resolutions. Partner Solutions