Puzzling AXI3 protocol signal capture during HDL development. - Puzzling AXI3 protocol signal capture during HDL development. Dear Intel and all, Could FAE or internal HPS or any stuff can help check if this is even possible? Can bvalid bresp return at the middle of the burst write? I think this is a violation of AXI3 protocol? Thank you Replies: Re: Puzzling AXI3 protocol signal capture during HDL development. I'm glad to hear that you were able to resolve your issue. Now, I will transitioning this thread to the community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Thank you and have a great day! Best Regards, Richard Tan Replies: Re: Puzzling AXI3 protocol signal capture during HDL development. Sorry for the noise. After debug it is a bead missing trigger a chain shifting on the bus.