TCPIP-1G/10G: 1G/10G TCP/IP Hardware Stack - The TCPIP-1G/10G core is a complete TCP/IP hardware protocol stack, enabling systems to connect to IP networks and exchange TCP data without a host processor. Acting as server or client, it… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to an Internet Protocol (IP) network and exchange data using the TCP protocol without requiring assistance from — or even the presence of — a system processor. The core acts either as a server or a client and, without assistance from the host system, it autonomously opens, maintains, and closes TCP connections. The system integrating the TCPIP-1G/10G core can configure network parameters and preferences by accessing its control registers, and the core is then able to receive and send data via streaming data interfaces. The highly configurable core can adapt to different applications and diverse system requirements. The maximum number of simultaneous TCP sessions is configurable at synthesis time; it can be as high as 32,768 for devices like data servers, or as small as 1 for edge devices requiring minimum silicon area and power. Further user options include implementing a DHCP client that allows the core to automatically be assigned an IP address, enabling or disabling support of the reassembly of out-of-order TCP packets data, and integrating a UDP hardware stack with multicast support (IGMPv3). Finally, users can choose the packet processing mode, either cut-through or store-and-forward. In cut-through mode, the payload data are delivered to the host system as they arrive without any internal packet buffering and before the packets’ integrity can be validated. As a result, the core operating in cut-through mode features extremely low latency and requires less memory, but it cannot reassemble out-of-order packets and it may deliver data that will subsequently be marked as corrupted. Under the store-and-forward mode of operation, the core will always deliver verified, in-order packets, but will have higher latency and require more memory resources. The TCPIP-1G/10G core is rigorously verified and available in RTL source or as a targeted FPGA netlist. Its deliverables include a testbench, synthesis, and simulation scripts, and comprehensive user documentation. Ethernet Aerospace Broadcast Consumer Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Defense Industrial Medical TCPIP-1G/10G: 1G/10G TCP/IP Hardware Stack Key Features 10/100/1000, 2.5G, and 10G Ethernet Transmit and Receive, TCP server or client with up to 32k simultaneous TCP sessions Offering Brief Yes Yes No Yes Encrypted Verilog Verilog Arria® V GX FPGA Arria® V GZ FPGA Arria® V ST SoC FPGA Arria® V SX SoC FPGA Cyclone® IV E FPGA Cyclone® IV GX FPGA Cyclone® V E FPGA Cyclone® V GT FPGA Cyclone® V GX FPGA Cyclone® V SE SoC FPGA Cyclone® V ST SoC FPGA Cyclone® V SX SoC FPGA Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel Agilex® 5 FPGAs and SoC FPGAs D-Series Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 7 FPGAs and SoC FPGAs F-Series Intel Agilex® 7 FPGAs and SoC FPGAs I-Series Intel Agilex® 7 FPGAs and SoC FPGAs M-Series Intel Agilex® 9 FPGAs and SoC FPGAs Direct RF-Series Intel® Arria® 10 GT FPGA Intel® Arria® 10 GX FPGA Intel® Arria® 10 SX SoC FPGA Intel® Cyclone® 10 GX FPGA Intel® Cyclone® 10 LP FPGA Intel® MAX® 10 FPGA Intel® Stratix® 10 AX SoC FPGA Intel® Stratix® 10 DX FPGA Intel® Stratix® 10 GX FPGA Intel® Stratix® 10 SX SoC FPGA Intel® Stratix® 10 TX FPGA Stratix® IV E FPGA Stratix® IV GX FPGA Stratix® V GS FPGA Stratix® V GX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U6hMAE What's Included Verilog/System Verilog, Encrypted Verilog/System Verilog, or FPGA netlist Ordering Information TPIP-1G/10G a1JUi0000049U6hMAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2025-10-31T20:59:43.000+0000 The TCPIP-1G/10G core is a complete TCP/IP hardware protocol stack, enabling systems to connect to IP networks and exchange TCP data without a host processor. Acting as server or client, it autonomously opens, maintains, and closes TCP connections. Network parameters are configured via control registers, while data is exchanged over streaming interfaces. The core is highly configurable: up to 32,768 simultaneous TCP sessions can be supported, or just one for minimal area designs. Options include a DHCP client, reassembly of out-of-order packets, and integration of a UDP hardware stack with IGMPv3 multicast. Users may select cut-through mode for ultra-low latency and minimal buffering, or store-and-forward mode for verified, in-order delivery. Available in RTL or FPGA netlist form, the core is rigorously verified and provided with testbench, synthesis/simulation scripts, and full documentation, making it ideal for applications ranging from servers to edge devices. Partner Solutions