LDPC for 5G NR (Silicon Proven IP for Altera Devices) - This IP core features a programmable LDPC decoder using the Min-Sum algorithm, designed for 5G NR performance. It supports HARQ with LLR accumulation and early iteration exit for enhanced decoding… Mobiveil, Inc.(a GlobalLogic company) is a fast-growing technology company headquartered in Santa Clara, California, specializing in Silicon Intellectual Properties (SIP), application platforms, and… Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Configurable 5G NR LDPC encoder/decoder IP compliant with 3GPP TS 38.212 (Rel-17), supporting Base Graphs 1 & 2, wide lifting sizes (2–384), early-termination, and runtime-configurable code length/rate for high-throughput, low-latency 5G designs. Technology-independent, system-validated LDPC core for 5G NR PDSCH/PUSCH that implements min-sum decoding with programmable internal/LLR widths, HARQ combining, per-block selectable CB length / code rate / base graph / max iterations, and early exit via concurrent parity checks. Deliverables include synthesizable parameterized Verilog, synthesis scripts, UVM testbench & regression, test-vector software, C++ bit-accurate model, and documentation. Throughput scales with iterations and parallelism (graphs provided at 400 MHz clk). Error Correction ASIC Proto Data Center Cloud (Public, Private, Hybrid) Data Center OEM (IHV, ISV, SI, VAR) Industrial Wireless LDPC for 5G NR (Silicon Proven IP for Altera Devices) Key Features Full support of 5G NR specification (38.212 v17) Offering Brief No No No No Encrypted Verilog Verilog Agilex™ 3 FPGA C-Series Agilex™ 5 FPGA D-Series Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Agilex™ 7 FPGA I-Series Agilex™ 7 FPGA M-Series Agilex™ 9 FPGA Direct RF-Series Arria® 10 GT FPGA Arria® 10 GX FPGA Arria® 10 SX FPGA Stratix® 10 AX FPGA Stratix® 10 DX FPGA Stratix® 10 GX FPGA Stratix® 10 SX FPGA Stratix® 10 TX FPGA Yes Yes 24.3.1 Offering Brief Production a1JUi0000049UJxMAM What's Included Synthesizable parametrized Verilog Ordering Information NA Direct a1JUi0000049UJxMAM Production Intellectual Property (IP) a1MUi00000BO8shMAD a1MUi00000BO8shMAD Select 2026-04-21T12:58:32.000+0000 This IP core features a programmable LDPC decoder using the Min-Sum algorithm, designed for 5G NR performance. It supports HARQ with LLR accumulation and early iteration exit for enhanced decoding efficiency. Runtime-configurable iterations and low latency make it ideal for 5G baseband integration. Partner Solutions