Why do I see a high Bit Error Rate (BER) when using the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in external loopback mode? - Why do I see a high Bit Error Rate (BER) when using the F-Tile PMA/FEC Direct PHY Intel® FPGA IP in external loopback mode? Description Due to a limitation of the default F-Tile PMA/FEC Direct PHY transmitter parameter setting, you will see high Bit Error Rate (BER) if the external loopback insertion loss is larger than 5 dB. The default transmitter parameters can work well only with insertion loss smaller than 5 dB. Resolution With the situation if the insertion loss is larger than 5 dB, you need to add optimal TX analog parameters in qsf file to avoid BER. Future application note will be updated to guide the debug. Custom Fields values: ['novalue'] Troubleshooting 15012286633 False ['Deterministic Latency PHY IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 22.3 ['Agilex™ 7 FPGA F-Series', 'Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['novalue']