Unexpected Timing Results in Design With Both ALTMEMPHY and UniPHY - Unexpected Timing Results in Design With Both ALTMEMPHY and UniPHY Description Projects using both DDR3 SDRAM Controller with ALTMEMPHY and QDR II/II SRAM Controller with UniPHY in the same design may experience unexpected timing results. This issue will be fixed in a future version of the DDR3 SDRAM Controller with ALTMEMPHY and the QDR II/II SRAM Controller with UniPHY. Resolution The workaround for this issue is to ensure that the project’s .qsf file lists the .sdc file for the DDR3 SDRAM Controller with ALTMEMPHY above the .sdc file for the QDR II/II SRAM Controller with UniPHY. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 11.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']