Why did Intel® Quartus® Prime Software return the "Critical Warning (16248): Pin XXXX is placed too close with ADC pins. I/O pins placed too near to ADC pins" warning message when I compiled my design using Intel® MAX® 10 FPGA with E144 package? - Why did Intel® Quartus® Prime Software return the "Critical Warning (16248): Pin XXXX is placed too close with ADC pins. I/O pins placed too near to ADC pins" warning message when I compiled my design using Intel® MAX® 10 FPGA with E144 package? Description Intel® Quartus® Prime Software will give a "Critical Warning (16248) Pin xxx is placed too close to Analog to Digital Converter (ADC) pins. I/O pins placed too near to ADC pins will cause performance degradation on ADC sampling" when you assigned IO pins located in IO Bank 1A, 1B, 2, 3, 5, 7 and 8 using Intel® MAX® 10 FPGA device with E144 package. Resolution You need to follow restriction rules as published in Intel® MAX® 10 General Purpose I/O User Guide Table 16 and Table 18 to avoid this Critical Warning message. Custom Fields values: ['novalue'] Troubleshooting 15015532473 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software QUARTUS-ALITE'] novalue No plan to fix ['MAX® 10 10 FPGAs'] ['novalue'] ['novalue'] ['novalue']