Does the Cyclone® 10 Native Phy Transceiver IP offer tx_pma_elecidle input port? - Does the Cyclone® 10 Native Phy Transceiver IP offer tx_pma_elecidle input port? Description Due to feature limitations, Native Phy Transceiver IP for Intel® Cyclone® 10 devices does not offer the option “Enable tx_pma_elecidle”. Hence tx_pma_elecidle input port is not offered in the IP. Resolution There is no workaround to force the transmitter into an electrical idle condition. Please use the transmitter reset pin, tx_analogreset, or tx_digitalreset to place the transmitter in reset instead of the tri-state condition. Custom Fields values: ['novalue'] Troubleshooting 2205694697 False ['Transceiver Native PHY Arria® 10 Cyclone® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 17.1 ['Cyclone® 10 GX FPGA', 'Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']