Why does the Intel FPGA VIP Suite Deinterlacer II IP product poor deinterlacing quality? - Why does the Intel FPGA VIP Suite Deinterlacer II IP product poor deinterlacing quality? Description Due to a problem with the Quartus® Prime v16.1 of VIP Suite Deinterlacer II IP, when using video-over-firm cadence detection and correction algorithm, you may experience poor deinterlacing quality and that is because of a swapped f0/f1 issue. Resolution The workaround in v16.1 is to create a custom block prior to the deinterlacer II IP to toggle bit 2 of the interlaced nibble of incoming Avalon-ST video control packets. This issue is fixed starting in Quartus® Prime v17.0. Custom Fields values: ['novalue'] Troubleshooting FB: 436150; True ['Deinterlacer II (4K HDR passthrough) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 16.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']