How do I prevent PLL output counter merging in Quartus® II 12.1 and later for Intel® Stratix®, Arria® V and Cyclone® V FPGA devices? - How do I prevent PLL output counter merging in Quartus® II 12.1 and later for Intel® Stratix®, Arria® V and Cyclone® V FPGA devices? Description In Quartus® II versions 12.1 and later, you can use the QSF variable UNFORCE_MERGE_PLL_OUTPUT_COUNTER to prevent the PLL output counters from merging in Stratix® V, Arria® V, or Cyclone® V devices. Resolution Below is an example of the assignment being made to a PLL output counter: set_instance_assignment -name UNFORCE_MERGE_PLL_OUTPUT_COUNTER ON -to "mypll:inst|mypll_0002:mypll_inst|altera_pll:altera_pll_i*” Related Articles How do I preserve the PLL output counter order or prevent PLL output counter merging for Stratix V, Arria V, and Cyclone V devices in the Quartus II software version 12.0 SP2 and earlier? Why are the fPLL C counters not updated correctly when dynamically reconfiguring an Altera_PLL using the Altera_PLL_Reconfig IP? Custom Fields values: ['novalue'] Troubleshooting N/A False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 12.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']