Why does PCIe® core return multiple unexpected completion data in response to the host's memory read request on Avalon-MM interface? - Why does PCIe® core return multiple unexpected completion data in response to the host's memory read request on Avalon-MM interface? Description This issue may be caused by mismatches between PCIe ® clock configuration and system clock connections in SOPC builder. When "Use PCIe core clock" field is selected in "Avalon® Clock Domain" under "Avalon" tab, the core expects application clock is the same as pcie_core_clk. So, if the user logic uses different clock source, the core may return multiple garbage data. In this case, you may see many assertions of TxsReadDataValid_o and TxsReadData_o on Avalon-MM interface with or without pending MRD requests. There are two ways to fix this issue: 1. If synchronous design is intended, select 'Use PCIe core clock" and connect pcie_core_clk to the rest of the application clocks. 2. If asynchronous design is desired, pick "Use Separate clock" and application clock can be connected to any clock source. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Cyclone® IV GX FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']